cystech electronics corp. spec. no. : c122n3 issued date : 2015.07.22 revised date : page no. : 1/9 MTB55N03KSN3 cystek product specification 30v n-channel enhancement mode mosfet MTB55N03KSN3 bv dss 30v 4.8a i d @ v gs =10v, t a =25 c features ? lower gate charge ? esd protected gate ? pb-free lead plating and halogen-free package equivalent circuit outline ordering information device package shipping MTB55N03KSN3-0-t1-g sot-23 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel MTB55N03KSN3 sot-23 d s g gate s source d drain g r dson(typ) @ v gs =10v, i d =4.2a 35m r dson(typ) @ v gs =4.5v, i d =2a 50m environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pcs / tape & reel,7? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c122n3 issued date : 2015.07.22 revised date : page no. : 2/9 MTB55N03KSN3 cystek product specification absolute maximum ratings (tc=25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 30 gate-source voltage v gs 16 v t a =25 c, v gs =10v 4.8 continuous drain current t a =70 c, v gs =10v i d 3.8 pulsed drain current i dm 20 (note 1 & 2) a t a =25 c 1.38 (note 3) power dissipation t a =70 c p d 0.88 (note 3) w operating junction and storage temperature tj, tstg -55 ~ +150 c thermal characteristics parameter symbol value unit thermal resistance, junction to ambient , max r ja 90 *2 thermal resistance, junction to case, max r jc 70 c/w note : 1. pulse width limited by maximum junction temperature. 2. duty cycle 1%. 3. surface mounted on 1 in2 copper pad of fr4 board, t 10s; 270 c/w when mounted on min. copper pad. electrical characteristics (t a =25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 30 - - v gs =0v, i d =250 a v gs(th) 1 - 2.5 v v ds =v gs , i d =250 a i gss - - 10 v gs =16v, v ds =0v - - 1 v ds =24v, v gs =0v i dss - - 10 a v ds =24v, v gs =0v, tj=55 c - 35 45 i d =4.2a, v gs =10v *r ds(on) 1 ! ! - 50 65 m i d =2a, v gs =4.5v *g fs 1 ! ! - 5.5 - s v ds =5v, i d =3.5a dynamic ciss - 171 - coss - 59 - crss - 35 - pf v ds =10v, v gs =0v, f=1mhz *t d(on) 1 ! ! 2 ! ! - 3.6 - *t r 1 ! ! 2 ! ! - 16 - *t d(off) 1 ! ! 2 ! ! - 11.4 - *t f 1 ! ! 2 ! ! - 4.4 - ns v ds =15v, i d =4.2a,v gs =10v, r g =3
cystech electronics corp. spec. no. : c122n3 issued date : 2015.07.22 revised date : page no. : 3/9 MTB55N03KSN3 cystek product specification *qg 1 2 - 2.7 - *qgs 1 2 - 0.9 - *qgd 1 2 - 0.8 - nc v ds =15v, i d =4.2a, v gs =4.5v source-drain diode i s - - 2 i sm 3 - - 8 a v sd 1 - 0.78 1 v i s =1a, v gs =0v trr 1 - 6.6 - ns qrr 1 - 2 - nc i f =4.2a, di f /dt=100a/ s 1 pulse test : pulse width ? 300 s, duty cycle ? 2% 2 independent of operating temperature 3 pulse width limited by maximum junction temperature recommended soldering footprint
cystech electronics corp. spec. no. : c122n3 issued date : 2015.07.22 revised date : page no. : 4/9 MTB55N03KSN3 cystek product specification typical characteristics typical output characteristics 0 4 8 12 16 20 012345 v ds , drain-source voltage(v) i d , drain current(a) 10v, 9v, 8v, 7v, v gs =3v 4v 5v 4.5v 3.5v brekdown voltage vs ambient temperature 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.01 0.1 1 10 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =10v v gs =3v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 50 100 150 200 250 300 350 400 024681 0 drain-source on-state resistance vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =4.2a v gs =10v, i d =4.2a r ds( on) @ tj=25c : 35 m
cystech electronics corp. spec. no. : c122n3 issued date : 2015.07.22 revised date : page no. : 5/9 MTB55N03KSN3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 i d , drain current(a) g fs , forward transfer admittance(s) pulsed ta=25c v ds =5v gate charge characteristics 0 2 4 6 8 10 01234567 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =4.8a v d s =15v maximum safe operating area 0.01 0.1 1 10 100 0.01 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 100ms 1ms 100 s t a =25c, tj=150c,v gs =10v r ja =90c/w, single pulse maximum drain current vs junctiontemperature 0 1 2 3 4 5 6 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =10v
cystech electronics corp. spec. no. : c122n3 issued date : 2015.07.22 revised date : page no. : 6/9 MTB55N03KSN3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 2 4 6 8 10 12 14 16 18 20 0246810 v gs , gate-source voltage(v) i d , drain current(a) v ds =10v power derating curve 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 50 100 150 200 t a , ambient temperature() p d , power dissipation(w) mounted on fr-4 board with 1 in 2 pad area transient thermal response curves 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 t 1 , square wave pulse duration(s) r(t), normalized transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =9 0c/w
cystech electronics corp. spec. no. : c122n3 issued date : 2015.07.22 revised date : page no. : 7/9 MTB55N03KSN3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c122n3 issued date : 2015.07.22 revised date : page no. : 8/9 MTB55N03KSN3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c122n3 issued date : 2015.07.22 revised date : page no. : 9/9 MTB55N03KSN3 cystek product specification sot-23 dimension millimeters inches millimeters inches dim min. max. min. max. marking: dim min. max. min. max. a 0.900 1.150 0.035 0.045 e1 2.250 2.550 0.089 0.100 a1 0.000 0.100 0.000 0.004 e 0.950 typ 0.037 typ a2 0.900 1.050 0.035 0.041 e1 1.800 2.000 0.071 0.079 b 0.300 0.500 0.012 0.020 l 0.550 ref 0.022 ref c 0.080 0.150 0.003 0.006 l1 0.300 0.500 0.012 0.020 d 2.800 3.000 0.110 0.118 0 8 0 8 e 1.200 1.400 0.047 0.055 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . te b53s xx date code style: pin 1.gate 2.source 3.drain 3-lead sot-23 plastic surface mounted package cystek package code: n3
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